================================================================================ Note 2.0 Block Mode DMA 1 reply JAWS::KAISER 560 lines 25-MAR-1985 09:14 -------------------------------------------------------------------------------- +---------------+ +-----------------+ | d i g i t a l | | uNOTE # 002 | +---------------+ +-----------------+ +----------------------------------------------------+-----------------+ | Title: Block Mode DMA | Date: 01-JUN-83 | +----------------------------------------------------+-----------------+ | Originator: Scott Tincher and Mike Collins | Page 1 of 11 | +----------------------------------------------------+-----------------+ What is Block Mode DMA? ----------------------- Block Mode DMA is a method of data transfer which increases throughput due to the reduced handshaking necessary over the Q-bus. In order to implement Block Mode DMA both the master and slave devices must understand the block Mode protocol. If either device does not have Block Mode capability the transfers proceed via standard DATI or DATO cycles. Conventional Direct Memory Access on the Q-bus ---------------------------------------------- Under conventional DMA operations, after a DMA device has become bus master, it begins the data transfers. This is accomplished by gating an address onto the bus followed by the data being transferred to or from the memory device. If more than one transfer is performed by the temporary bus master, the address portion of the cycle must be repeated for each data transfer. Block Mode Direct Memory Access on the Q-bus -------------------------------------------- Under block Mode DMA operations an address cycle is followed by multiple word transfers to sequential addresses. Therefore data throughput is increased due to the elimination of the address portion of each transfer after the initial transfer. There are two types of block Mode transfer, DATBI (input) and DATBO (output). An overview of what occurs during each type of block Mode transfer is outlined in figures 1 (DATBI, Block Mode input) and 2 (DATBO, block mode output). In the following discussion the signal prefix T(Transmit) indicates a bus driver input and the signal prefix R(Receive) indicates a bus receiver output. Page 2 DATBI Bus Cycle --------------- Before a DATBI block mode transfer can occur the DMA bus master device must request control of the bus. This occurs under conventional Q-bus protocol. o REQUEST BUS The bus master device requests control of the bus by asserting TDMR. o GRANT BUS CONTROL The bus arbitration logic in the CPU asserts the DMA grant signal TDMGO 0 nsec minimum after TDMR is received and 0 nsec minimum after RSACK negates (if a DMA device was previous bus master). o ACKNOWLEDGE BUS MASTERSHIP The DMA bus master device asserts TSACK 0 nsec minimum after receiving RDMGI, 0 nsec minimum after the negation of RSYNC and 0 nsec minimum after the negation of RRPLY. The DMA bus master device negates TDMR 0 nsec minimum after the assertion of TSACK. o TERMINATE GRANT SEQUENCE The bus arbitration logic in the CPU negates TDMGO 0 nsec minimum after receiving RSACK. The bus arbitration logic will also negate TDMGO if RDMR negates or if RSACK fails to assert within 10 usec ('no SACK timeout'). o EXECUTE A BLOCK MODE DATBI TRANSFER o ADDRESS DEVICE MEMORY a) The address is asserted by the bus master on TADDR<21:00> along with the negation of TWTBT. b) The bus master asserts TSYNC 150 nsec minimum after gating the address onto the bus. o DECODE ADDRESS The appropriate memory device recognizes that it must respond to the address on the bus. o REQUEST DATA a) The address is removed by the bus master from TADDR<21:00> 100 nsec minimum after the assertion of TSYNC. b) The bus master asserts the first TDIN 100 nsec minimum after asserting TSYNC. Page 3 c) The bus master asserts TBS7 50 nsec maximum after asserting TDIN for the first time. TBS7 remains asserted until 50 nsec maximum after the assertion of TDIN for the last time. In each case, TBS7 can be asserted or negated as soon as the conditions for asserting TDIN are met. The assertion of TBS7 indicates the bus master is requesting another read cycle after the current read cycle. o SEND DATA a) The bus slave asserts TRPLY 0 nsec minimum (8000 nsec maximum to avoid a bus timeout) after receiving RDIN. b) The bus slave asserts TREF concurrent with TRPLY if, and only if, it is a block mode device which can support another RDIN after the current RDIN. NOTE Block mode transfers must not cross 16 word boundaries c) The bus slave gates TDATA<15:00> onto the bus 0 nsec minimum after receiving RDIN and 125 nsec maximum after the assertion of TRPLY. o TERMINATE INPUT TRANSFER a) The bus master receives stable RDATA<15:00> from 200 nsec maximum after receiving RRPLY until 20 nsec minimum after the negation of RDIN. (The 20 nsec minimum represents total minimum receiver delays for RDIN at the slave and RDATA<15:00> at the master.) b) The bus master negates TDIN 200 nsec minimum after receiving RRPLY. o OPERATION COMPLETED a) The bus slave negates TRPLY 0 nsec minimum after receiving the negation of RDIN. b) If RBS7 and TREF are both asserted when TRPLY negates, the bus slave prepares for another DIN cycle. RBS7 is stable from 125 nsec after RDIN is received until 150 nsec after TRPLY negates. c) If TBS7 and RREF were both asserted when TDIN negated, the bus master asserts TDIN 150 nsec minimum after receiving the negation of RRPLY and continues with timing relationship 'SEND DATA' above. RREF is stable from 75 nsec after RRPLY asserts until 20 nsec minimum after TDIN negates. (The 0 nsec minimum represents total minimum receiver delays for RDIN at the slave and RREF at the master.) Page 4 NOTE The bus master must limit itself to not more than eight transfers unless it monitors RDMR. If it monitors RDMR, it may perform up to 16 transfers as long as RDMR is not asserted at the end of the seventh transfer. o TERMINATE BUS CYCLE a) If RBS7 and TREF were not both asserted when TRPLY negated, the bus slave removes TDATA<15:00> from the bus 0 nsec minimum and 100 nsec maximum after negating TRPLY. b) If TBS7 and RREF were not both asserted when TDIN negated the bus master negates TSYNC 250 nsec minimum after receiving the last assertion of RRPLY and 0 nsec minimum after the negation of that RRPLY. o RELEASE THE BUS a) The DMA bus master negates TSACK 0 nsec after negation of the last RRPLY. b) The DMA bus master negates TSYNC 300 nsec maximum after it negates TSACK. c) The DMA bus master must remove RDATA<15:00>, TBS7, and TWTBT from the bus 100 nsec maximum after clearing TSYNC. o RESUME PROCESSOR OPERATION The bus arbitration logic in the CPU enables processor-generated TSYNC or will issue another bus grant (TDMGO) if RDMR is asserted. Page 5 Figure 1 - DATBI CYCLE ---------------------- PROCESSOR I/O DEVICE MEMORY --------- ---------- ------ +- Request Bus | ----------- | Assert TDMR Grant Bus Control <--+ ----------------- . Near end of the current bus cycle (RRPLY is negated) assert TDMGO and inhibit new processor generated TSYNC for the duration of the DMA operation | | +----> Acknowledge Bus Mastership -------------------------- . Receive RDMGO . Wait for negation of RSYNC and RRPLY . Assert TSACK +--------- . Negate TDMR | V Terminate Grant Sequence ------------------------ . Negated RDMGO and wait for DMA operation to be completed | | +--> Execute a Block Mode DMA ------------------------ (DATBI) Data Transfer --------------------- . . . Address Device Memory --------------------- . Assert address on TADDR<21:00> . Assert TSYNC . Negate TWTBT -------+ | +---> Decode Address -------------- . Store "Device Selected" operation Page 6 Figure 1 - DATBI CYCLE (continued) ---------------------------------- PROCESSOR I/O DEVICE MEMORY --------- ---------- ------ +----> Request Data | ------------ | . Remove address from TADDR<21:00> | . Assert TDIN | . Assert TBS7 (request for an | additional DIN cycle after | the current one | | | +-----------> Send Data | --------- | . Data on TDATA<15:00> | . Assert TRPLY | . Assert TREF (to | indicates block | mode capability) | | | Terminate Input <---------+ | --------------- | Transfer | -------- | . Accept data and respond | by negating TDIN | | | +------> Operation Completed | ------------------- | . Negate TRPLY | | | +-----------+ | yes | are | +------------------------|RBS7 & TREF| | Asserted | | ? | +-----------+ | no Terminate Bus Cycle <------+ ------------------- and Release the Bus ------------------- . Negate TSACK . Negate TSYNC . Remove TDAL, TBS7, and, +----- TWTBT from the Bus | V Resume Processor Operation -------------------------- . Enable processor generated TSYNC or issue another grant if RDMR is asserted Page 7 DATBO Bus Cycle --------------- DATBO Bus cycles Before a block mode transfer can occur the DMA bus master device must request control of the bus. This occurs under conventional Q-bus protocol. o REQUEST BUS The bus master device requests control of the bus by asserting TDMR. o GRANT BUS CONTROL The bus arbitration logic in the CPU asserts the DMA grant signal TDMGO 0 nsec minimum after RDMR is received and 0 nsec minimum after TSACK negates (if a DMA device was previous bus master). o ACKNOWLEDGE BUS MASTERSHIP The DMA bus master device asserts TSACK 0 nsec minimum after receiving RDMGI, 0 nsec minimum after the negation of RSYNC and 0 nsec minimum after the negation of RRPLY. The DMA bus master device negates TDMR 0 nsec minimum after the assertion of TSACK. o TERMINATE GRANT SEQUENCE The bus arbitration logic in the CPU negates TDMGO 0 nsec minimum after receiving RSACK. The bus arbitration logic will also negate TDMGO if RDMR negates or if RSACK fails to assert within 10 usec ('no SACK timeout'). o EXECUTE A BLOCK MODE DATBO TRANSFER o ADDRESS DEVICE MEMORY a) The address is asserted by the bus master on TADDR<21:00> along with the assertion of TWTBT. b) The bus master asserts TSYNC 150 nsec minimum after gating the address onto the bus. o DECODE ADDRESS The appropriate memory device recognizes that it must respond to the address on the bus. o SEND DATA a) The bus master gates TDATA<15:00> along with TWTBT 100 nsec minimum after the assertion of TSYNC. TWTBT is negated. b) The bus master asserts the first TDOUT 100 nsec minimum after gating TDATA<15:00>. NOTE During DATBO cycles TBS7 is undefined o RECEIVE DATA a) The bus slave receives stable data on RDATA<15:00> from Page 8 25 nsec minimum before receiving RDOUT until 25 nsec minimum after receiving the negation of RDOUT. b) The bus slave asserts TRPLY 0 nsec minimum after receiving RDOUT. c) The bus slave asserts TREF concurrent with TRPLY if, and only if, it is a block mode device which can support another RDOUT after the current RDOUT. NOTE Blockmode transfers must not cross 16 word boundaries o TERMINATE OUTPUT TRANSFER The bus master negates TDOUT 150 nsec minimum after receiving RRPLY. o OPERATION COMPLETED a) The bus slave negates TRPLY 0 nsec minimum after receiving the negation of RDOUT. b) If RREF was asserted when TDOUT negated and if the bus master wants to transfer another word, the bus master gates the new data on TDATA<15:00> 100 nsec minimum after negating TDOUT. RREF is stable from 75 nsec maximum after RRPLY asserts until 20 nsec minimum after RDOUT negates. (The 20 nsec minimum represents minimum receiver delays for RDOUT at the slave and RREF at the master). c) The bus master asserts TDOUT 100 nsec minimum after gating new data on TDATA<15:00> and 150 nsec minimum after receiving the negation of RRPLY. The cycle continues with the timing relationship in 'RECEIVE DATA' above. NOTE The bus master must limit itself to not more than eight transfers unless it monitors RDMR. If it monitors RDMR, it may perform up to 16 transfers as long as RDMR is not asserted at the end of the seventh transfer. o TERMINATE BUS CYCLE a) If RREF was not asserted when RRPLY negated or if the bus master has no additional data to transfer, the bus master removes data on TDATA<15:00> from the bus 100 nsec minimum after negating TDOUT. b) If RREF was not asserted when TDOUT negated the bus master negates TSYNC 275 nsec minimum after receiving the last RRPLY and 0 nsec minimum after the the negation of the last RRPLY. Page 9 o RELEASE THE BUS a) The DMA bus master negates TSACK 0 nsec after negation of the last RRPLY. b) The DMA bus master negates TSYNC 300 nsec maximum after it negates TSACK. c) The DMA bus master must remove TDATA, TBS7, and TWTBT from the bus 100 nsec maximum after clearing TSYNC. o RESUME PROCESSOR OPERATION The bus arbitration logic in the CPU enables processor-generated TSYNC or will issue another bus grant (TDMGO) if RDMR is asserted. Page 10 Figure 2 - DATBO CYCLE ---------------------- PROCESSOR I/O DEVICE MEMORY --------- ---------- ------ +- Request Bus | ----------- | . Assert TDMR Grant Bus Control <----+ ----------------- . Near the end of the current bus cycle (RRPLY is negated) assert TDMGO and inhibit new processor generated TSYNC for the duration of the DMA operation. | | +-------> Acknowledge Bus Mastership -------------------------- . Receive RDMG . Wait for negation of RSYNC and RRPLY . Assert TSACK +-------- . Negate TDMR | V Terminate Grant Sequence ------------------------ . Negate TDMGO and wait for DMA operation to be completed. | +---------> Execute A Block Mode DMA ------------------------- (DATBO) Data Transfer --------------------- . . . Address Memory -------------- . Assert Address on TADDR<21:00> . Assert TWTBT . Assert TSYNC ------+ | +-----> Decode Address -------------- . Address match selects device Page 11 Figure 2 - DATBO CYCLE (continued) ---------------------------------- PROCESSOR I/O DEVICE MEMORY --------- ---------- ------ +----> Send Data | --------- | . Assert TDATA <15:00> | . Negate TWTBT | . Assert TDOUT ----+ | | | +--> Receive Data | ------------ | . Accept data and | RWTBT | . Assert TRPLY | . Assert TREF | (Indicates block | mode capability) | | | | | Terminate Output Transfer <-----+ | ------------------------- | | . Negate TDOUT --+ | | | +--> Operation Completed | ------------------- | . Negate TRPLY | | | +------------------+ +----------+ yes | | Does Master | yes | is RREF | +-| Wish to Transfer |<-----|Asserted ?| | More Data ? | +----------+ +------------------+ | no | | Terminate Bus Cycle and <-------+ ----------------------- Release the Bus --------------- . Negate TSACK . Negate TSYNC +----- . Remove TDAL, TDAL,TBS7, and TWTBT | from the Bus | | Resume Processor Operation -------------------------- . Enable processor generated TSYNC (processor is bus master) or issue another grant if RDMR is asserted ================================================================================ Note 2.1 Block Mode DMA 1 of 1 MOTHER::FRAZIER 12 lines 4-JUN-1985 14:48 -------------------------------------------------------------------------------- I'd like to point out a potential problem. The MXV11-B has been promoted as a usable companion for the KDJ11-AA. However the MXV11-B does NOT support "Block Mode" transfers. The MXV11-B also must have a starting address within the first 265kb. So now the ring buffer for the RQDX1/2 is in non-block mode memory. The results are predictably disastrous. James